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Dual PCI 2.2 Hot-Swap Controllers
2  _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
+12VIN to GND ...................................................-0.3V to +14.0V
-12VIN to GND........................................................-14V to +0.3V
-12VO_ to GND......................................+0.3V to (V
-12VIN
- 0.3V)
+12VO_, 3.3VGATE_, 5VGATE_
to GND..................................................-0.3V to (V
+12VIN
+ 0.3V)
Any Other Pin to GND ...........................................-0.3V to +6.0V
Continuous Power Dissipation (T
A
= +70癈)
28-Pin TSSOP (derate 23.8mW/癈 above +70癈) ...........1.9W
Operating Temperature Ranges:
MAX591_U_ _ ......................................................0癈 to +85癈
MAX591_A U_ _...................................................0癈 to +85癈
MAX591_E_ _....................................................-40癈 to +85癈
MAX591_ AE_ _ ................................................-40癈 to +85癈
Maximum Junction Temperature .....................................+150癈
Storage Temperature Range.............................-65癈 to +150癈
Lead Temperature (soldering, 10s).................................+300癈
ELECTRICAL CHARACTERISTICS
(V
-12VIN
= -12V, V
+12VIN
= +12V, V
3.3VAUXIN
= +3.3V, V
ON_
= V
AUXON_
= +5V, T
A
= T
MIN
to T
MAX
, unless otherwise specified.
Typical values are at T
A
= +25癈.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Main Supply Input Voltage
Range
V
+12VIN
10.8
12
13.2
V
Main Supply Undervoltage
Lockout (UVLO)
V
+12UVLO
V
+12VIN
 rising
9.6
10
10.8
V
Main Supply UVLO Hysteresis
V
UVLO, HYS
100
mV
Main Input UVLO Delay Time
t
DEG, UVLO
Figures 1 and 2 (Note 1)
1.6
ms
Supply Current
I
Q
2.5
5.0
mA
+3.3V SUPPLY CONTROL
Gate Charge Current
I
3.3VGATE_ CHG
V
3 .3 V
GAT E
_ = + 6V , V
3 .3 V S E
N _
 = + 3.3V ,
V
3 .3 V
O
_ = + 3.3V
5
15
30
礎
Gate Discharge Current
I
3.3VGATE_ DIS
V
3.3VGATE
_ = +12V, V
ON_
= 0V
50
150
250
礎
Gate High Voltage
V
3.3VGATE_ HIGH
I
3.3VGATE
_ = 1礎
V
+12VIN
 -
0.5
V
+12VIN
V
Gate Low Voltage
V
3.3VGATE_ LOW
I
3.3VGATE
_ = 1礎, V
ON
_ = 0V
0.1
0.4
V
3.3VO_ Input Bias Current
I
3.3VO_, BIAS
V
3.3VO
_ = +3.3V
20
礎
3.3VO_ Internal Pulldown
R
PD
V
ON
_ = 0V
1
k&
3.3VSEN_ Input Bias Current
I
3.3VSEN_ BIAS
V
3.3VSEN
_ = +3.3V
10
礎
Current-Limit Threshold
V
3.3V, LIM
V
3.3VGATE
_ = +6V
41
46
51
mV
Output Undervoltage Threshold
V
3.3VIN, UV
V
3.3VGATE
_ falling
2.79
2.89
2.99
V
Output Undervoltage Threshold
Hysteresis
30
mV
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